Many high performance circuits such as, for example, microprocessors, use static flip-flops. Generally, these static flip-flops are master-slave edge-triggered flip-flops. However, as the speeds of these high performance circuits increase, the use of conventional master-slave edge-triggered flip-flops becomes unattractive because these conventional flip-flops are relatively slow and require both the true and complement of the clock signal. Typically, these conventional static flip-flops require special clock buffers or "headers" to generate complementary clock signals.
FIG. 1 is a schematic diagram of a typical conventional master-slave rising edge-triggered static flip-flop 100. The flip-flop 100 includes a master stage 101 driving a slave stage 103. The master stage 101 has a conventional transmission gate 105 having an input lead 106 coupled to receive a data signal D. As is well known, the transmission gate 105 of the master stage is controlled to transmit the received data signal D by the true and complementary clock signals CK and CKB respectively received by the p-channel and n-channel devices implementing the transmission gate 105. Thus, the master stage's transmission gate 105 is controlled to pass the data signal D prior to a rising edge (i.e., while the clock signal CK is at a logic low level).
A conventional latch 107, implemented with the inverters INV1 and INV2, has an input lead connected to an output lead 108 of the transmission gate 105. Thus, while the clock signal CK is at a logic low level, the latch 107 inverts the data signal D and latches the inverted data signal on the output lead of the master stage 101. Then, at the rising edge of the clock signal CK, the transmission gate 105 is no longer conductive, while the latch 107 continues to output the complement of the data signal D at the time of the rising edge.
The slave stage 103 also includes a transmission gate and a latch. However, the transmission gate 109 of the slave stage 103 is configured to be conductive when the transmission gate 105 is non-conductive and vice versa. Typically, the transmission gate of the slave stage is connected to receive the clock signals CK and CKB respectively at the gates of the n-channel and p-channel devices implementing the transmission gate 109. Thus, before the rising edge of the clock signal CK, the transmission gate 109 is non-conductive. However, at the rising edge of the clock signal CK, the transmission gate 109 transmits the latched output signal of the master stage 101 (i.e., the complement of the data signal D at the time of the rising edge) to a conventional output latch 111, implemented with the inverters INV3 and INV4. Thus, the output latch 111 outputs a signal Q equivalent to the data signal D at the time of the rising edge for the rest of the cycle. Counting the delay of the transmission gates as 1/2 of a typical gate delay, the conventional flip-flop 100 has a latency of about three gate delays, measured from the set-up time of the data signal D (prior to the rising edge of the clock signal CK) to the transition of the flip-flop output signal Q after the rising edge of the clock signal CK. Of course, any improvement in speed of the flip-flop is desirable for most applications.
In addition, the conventional master-slave flip-flop 100 may be modified for testing purposes to include scan test capability, which is well known in the art of flip-flops. For example, in a typical scan design testing scheme, test (or scan) data is loaded into a set of scan flip-flops and then the logic circuitry receiving the scan data is clocked for one cycle. Another set of scan flip-flops stores the output (or capture) data from this logic circuitry, which are then compared to the expected result. If the capture data does not match the expected result, then a possible fault has been detected.
However, the scan functionality typically results in either increased complexity or a speed penalty. For example, as shown in FIG. 1A, in one conventional scan flip-flop design, a scan flip-flop 118 includes a two-input multiplexer formed from the master stage 101 of the flip-flop 100 (FIG. 1). In particular, the scan flip-flop 118 has a master stage 120 identical to the master stage 101 (FIG. 1) with a second transmission gate 122 connected in parallel to the transmission gate 105. The second transmission gate 122 is connected to receive a scan-input signal SI and is clocked by scan clock signals SCK and SCKB. The scan clock signals are provided to the flip-flop 118 only during the scan mode and, conversely, the clock signals CK and CKB are provided to the flip-flop 118 only during the "normal" operational mode.
However, transmission gates typically are relatively large in size, which increases the cost of the flip-flop and occupies area that could otherwise be used for other devices. In addition, transmission gates typically represent a large capacitive load to the signal driver, which therefore causes the driver to be relatively large in size and power dissipation. In this example, the scan flip-flop 118 includes three transmission gates (i.e., the transmission gates 105 and 122 in the master stage 120 and a transmission gate in the slave stage) and, thus, is relatively slow while having a relatively large size and power dissipation. Accordingly, there is a need for a scan flip-flop that is fast while minimizing the size and power dissipation.